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Version: nginx-1.15.12 ]​[ nginx-1.16.0 ]​

0001 
0002 /*
0003  * Copyright (C) Igor Sysoev
0004  * Copyright (C) Nginx, Inc.
0005  */
0006 
0007 
0008 #if (NGX_SMP)
0009 #define NGX_SMP_LOCK  "lock;"
0010 #else
0011 #define NGX_SMP_LOCK
0012 #endif
0013 
0014 
0015 /*
0016  * "cmpxchgl  r, [m]":
0017  *
0018  *     if (eax == [m]) {
0019  *         zf = 1;
0020  *         [m] = r;
0021  *     } else {
0022  *         zf = 0;
0023  *         eax = [m];
0024  *     }
0025  *
0026  *
0027  * The "r" means the general register.
0028  * The "=a" and "a" are the %eax register.
0029  * Although we can return result in any register, we use "a" because it is
0030  * used in cmpxchgl anyway.  The result is actually in %al but not in %eax,
0031  * however, as the code is inlined gcc can test %al as well as %eax,
0032  * and icc adds "movzbl %al, %eax" by itself.
0033  *
0034  * The "cc" means that flags were changed.
0035  */
0036 
0037 static ngx_inline ngx_atomic_uint_t
0038 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
0039     ngx_atomic_uint_t set)
0040 {
0041     u_char  res;
0042 
0043     __asm__ volatile (
0044 
0045          NGX_SMP_LOCK
0046     "    cmpxchgl  %3, %1;   "
0047     "    sete      %0;       "
0048 
0049     : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory");
0050 
0051     return res;
0052 }
0053 
0054 
0055 /*
0056  * "xaddl  r, [m]":
0057  *
0058  *     temp = [m];
0059  *     [m] += r;
0060  *     r = temp;
0061  *
0062  *
0063  * The "+r" means the general register.
0064  * The "cc" means that flags were changed.
0065  */
0066 
0067 
0068 #if !(( __GNUC__ == 2 && __GNUC_MINOR__ <= 7 ) || ( __INTEL_COMPILER >= 800 ))
0069 
0070 /*
0071  * icc 8.1 and 9.0 compile broken code with -march=pentium4 option:
0072  * ngx_atomic_fetch_add() always return the input "add" value,
0073  * so we use the gcc 2.7 version.
0074  *
0075  * icc 8.1 and 9.0 with -march=pentiumpro option or icc 7.1 compile
0076  * correct code.
0077  */
0078 
0079 static ngx_inline ngx_atomic_int_t
0080 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
0081 {
0082     __asm__ volatile (
0083 
0084          NGX_SMP_LOCK
0085     "    xaddl  %0, %1;   "
0086 
0087     : "+r" (add) : "m" (*value) : "cc", "memory");
0088 
0089     return add;
0090 }
0091 
0092 
0093 #else
0094 
0095 /*
0096  * gcc 2.7 does not support "+r", so we have to use the fixed
0097  * %eax ("=a" and "a") and this adds two superfluous instructions in the end
0098  * of code, something like this: "mov %eax, %edx / mov %edx, %eax".
0099  */
0100 
0101 static ngx_inline ngx_atomic_int_t
0102 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
0103 {
0104     ngx_atomic_uint_t  old;
0105 
0106     __asm__ volatile (
0107 
0108          NGX_SMP_LOCK
0109     "    xaddl  %2, %1;   "
0110 
0111     : "=a" (old) : "m" (*value), "a" (add) : "cc", "memory");
0112 
0113     return old;
0114 }
0115 
0116 #endif
0117 
0118 
0119 /*
0120  * on x86 the write operations go in a program order, so we need only
0121  * to disable the gcc reorder optimizations
0122  */
0123 
0124 #define ngx_memory_barrier()    __asm__ volatile ("" ::: "memory")
0125 
0126 /* old "as" does not support "pause" opcode */
0127 #define ngx_cpu_pause()         __asm__ (".byte 0xf3, 0x90")