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Version: nginx-1.15.11 ]​[ nginx-1.14.2 ]​

0001 
0002 /*
0003  * Copyright (C) Igor Sysoev
0004  * Copyright (C) Nginx, Inc.
0005  */
0006 
0007 
0008 #if (NGX_SMP)
0009 #define NGX_SMP_LOCK  "lock;"
0010 #else
0011 #define NGX_SMP_LOCK
0012 #endif
0013 
0014 
0015 /*
0016  * "cmpxchgq  r, [m]":
0017  *
0018  *     if (rax == [m]) {
0019  *         zf = 1;
0020  *         [m] = r;
0021  *     } else {
0022  *         zf = 0;
0023  *         rax = [m];
0024  *     }
0025  *
0026  *
0027  * The "r" is any register, %rax (%r0) - %r16.
0028  * The "=a" and "a" are the %rax register.
0029  * Although we can return result in any register, we use "a" because it is
0030  * used in cmpxchgq anyway.  The result is actually in %al but not in $rax,
0031  * however as the code is inlined gcc can test %al as well as %rax.
0032  *
0033  * The "cc" means that flags were changed.
0034  */
0035 
0036 static ngx_inline ngx_atomic_uint_t
0037 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
0038     ngx_atomic_uint_t set)
0039 {
0040     u_char  res;
0041 
0042     __asm__ volatile (
0043 
0044          NGX_SMP_LOCK
0045     "    cmpxchgq  %3, %1;   "
0046     "    sete      %0;       "
0047 
0048     : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory");
0049 
0050     return res;
0051 }
0052 
0053 
0054 /*
0055  * "xaddq  r, [m]":
0056  *
0057  *     temp = [m];
0058  *     [m] += r;
0059  *     r = temp;
0060  *
0061  *
0062  * The "+r" is any register, %rax (%r0) - %r16.
0063  * The "cc" means that flags were changed.
0064  */
0065 
0066 static ngx_inline ngx_atomic_int_t
0067 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
0068 {
0069     __asm__ volatile (
0070 
0071          NGX_SMP_LOCK
0072     "    xaddq  %0, %1;   "
0073 
0074     : "+r" (add) : "m" (*value) : "cc", "memory");
0075 
0076     return add;
0077 }
0078 
0079 
0080 #define ngx_memory_barrier()    __asm__ volatile ("" ::: "memory")
0081 
0082 #define ngx_cpu_pause()         __asm__ ("pause")